As integrated circuits increase in complexity, systems and methods must be capable of testing them to their limits, if the functionality under expected operating conditions is to be proven. Many advanced integrated circuits are operating too fast and are becoming too complex to be tested only by external test equipment. In place of external test equipment, more and more testing is being performed by circuitry implemented on the integrated circuit itself as built-in-self-test (BIST) circuitry. However, as the BIST circuitry becomes more complex, new systems and methods are needed to assure that integrated circuit functions are tested to the full limits they are required to operate.
One type of data receiver used in integrated circuits is capable of receiving data bit signals from an incoming data line without requiring a separate clock signal to be transmitted on a separate line from the data line. Such data receiver is known as a Clock and Data Recovery Circuit (“CDR”) because the phase and frequency of the clock signal is recovered from the data line signal(s) along with the transmitted data bits.
A particular requirement of an on-chip data receiver, including a clock and data recovery circuit, is that it be tolerant to signal jitter. FIG. 1 shows bit signals 200 as they appear at the input to a receiver. The bit signals 200 include two complementary signals which swing at periodic intervals, according to their data content. In such example, the bit time, defined as the average time between signal transitions, is 400 picoseconds (pS). However, due to the characteristics of the transmitter and the transmission line, and other influences between the transmitter and the CDR, the signal transitions 202 have jitter. The jitter is manifested as a period of time 203 during which the state of the complementary data signals is uncertain because of variations in the arrival of the signal transitions. Because of the jitter, the clock signal used to sample the data signal is best adjusted to a phase 204 which lies at the midpoint of the bit time between transitions. In operation, this sampling clock signal must be continually adjusted in phase in order to match the transmitted clock signal. As the incoming data signal varies, it may often take several clock cycles to adjust the sampling clock signal to the correct phase at the midpoint between signal transitions. High frequency signal jitter which occurs over fewer clock cycles must be tolerated by assuring that there be large enough timing margins between the ideal sampling clock phase 204 at the bit time midpoint, and the jitter in the left and right transitions of the data signal.
In order to assure satisfactory operation under expected conditions, a robust system and method is needed to test the jitter tolerance of a clock and data recovery circuit.